Diode-array target including isolating low resistivity regions

ABSTRACT

The specification describes an improved diode array target for an electron beam storage tube. The target is an improvement of the device described in U.S. Pat. Nos. 3,403,284 and 3,419,746. The target is modified so as to include an N layer in the surface region of the semiconductor substrate between the diodes. This layer serves to isolate the diodes, to reduce the dark current generation, and to increase the resolution of the camera tube.

tates atet [is] 3,676,727 Dalton et a1. July 11, 1972 s41 DIODE-ARRAYTARGET INCLUDING 3,483,421 12/1969 Hogan ..313/66 x ISOLATING LQWRESISTIVITY 3,517,246 6/1970 Chester et a]... ..314/66 3,548,233 12/1970Cave et a1 313/65 AB REGIONS 3,252,030 5/1966 Cawein.... ..313/66 [72]Inventors: John Vincent Dalton, Oldwick, N..l.; Ed- 3,307,984 3/1967Frazier ..317/234 X ward Franklin Labuda, Allentown, Pa. 3,309,2453/1967 l-laenichen ...317/235 AG Assignee: Bell Telephone LaboratoriesIncorporated, 3,403,284 9/1968 Buck et a1. ..250/21 1 .1 X

Murray Primary ExaminerRobert Sega] [22] Filed: March 30, 1970Attorney-R. J. Guenther and Arthur J. Torsiglieri [21] App]. No.: 23,871[57] ABSTRACT The specification describes an improved diode array targetfor if 33$ an electron beam storage tube. The target is an improvement iJ 1 31'3/65 AB 66 of the device described in us. Pat. Nos. 3,403,284 andle 0 arc 3,419,746 The target is modified so as to include an N+ layer56 R fe Cited in the surface region of the semiconductor substratebetween 1 e the diodes. This layer serves to isolate the diodes, toreduce UNITED STATES PATENTS the dark current generation, and toincrease the resolution of the camera tube. 3,419,746 12/1968 Crowell eta1. ..313/65 AB 3,448,349 6/1969 Sumner ..317/234 5 Claims, 5 Drawingfigures PKTE'N TEDJUL 1 1 I972 FIG.

FIG, 3A (PRIOR ART) FIG 3B A w B .AA 1/ 0L m III 0 \t s x T 2 W 1% W a wPJLINPFE ATTORNEY DIODE-ARRAY TARGET INCLUDING ISOLATING LOW RESISTIVITYREGIONS This invention relates to semiconductor diode-array targets forelectron beam camera tubes.

The diode-array camera tube described and claimed in U.S. Pat. No.3,403,284 issued to T. M. Buck, M. H. Crowell and E. I. Gordon on Sept.24, 1968 and US. Pat. No. 3,419,746 issued to M. H. Crowell, J. V.Dalton, E. I. Gordon and E. F. Labuda on Dec. 31, 1968 is well known inthe art and is an established commercial device. However, efforts arebeing continued to improve its performance, and the invention describedherein provides three improvements in performance. It reduces the darkcurrent of the camera tube; it provides better isolation between diodes;and it improves the resolution of the camera tube.

In all camera tubes that relay on a charge storage mechanism the problemof dark current is inherent. Techniques for reducing dark current arecontinually being sought.

The major source of dark current in the diode-array target is usuallythe recombination-generation centers located at the silicon-silicondioxide interface. These centers contribute to the dark current onlywhen the semiconductor at this interface is depleted.

Assume that a voltage V is the target voltage at which the semiconductorstarts to deplete. For target voltages less than V,,, the dark currentis low, the surface is not depleted, and the dark current in thisvoltage range is due to recombinationgeneration centers located in thebulk of the semiconductor. As the target voltage is raised above V thereis a rapid increase in dark current followed by a sharp saturation at avoltage V For voltages above V the surface is depleting and the rapidincrease in dark current is due to the recombinationgeneration centerslocated at the silicon-silicon dioxide interface which can nowcontribute to the dark current. The dark current saturates when theentire interface is fully depleted and all the surfacerecombination-generation centers are contributing. Note that anytechnique which leads to a higher saturation voltage V, will for lowertarget voltages yield a lower dark current.

Another problem that can occur for target voltages greater than V, isthat isolation between diodes can be lost if one of the diodes can actas a source of minority carriers. For instance, this could happen if adiode has a very high leakage current due to some sort of defect in thevicinity of the diode. Such a diode would not remain reverse biasedduring the frame time and could act as a source of minority carriers,the result being the formation of a channel between thiS diode and otherneighboring diodes. This effect will be recognized as similar to thatwhich occurs in the well-known insulated gate field effect transistorwhen the source and drain are electrically connected together by achannel by the application of an appropriate gate voltage. Again anytechnique which leads to a higher V will tend to inhibit this problem.

According to the invention, the foregoing difficulties are substantiallyovercome by diffusing additional impurities into those surface regionsof the semiconductor surrounding the diodes. This low resistivitysurface layer has the effect of increasing the saturation voltage Vthereby reducing the dark current for voltages less than V, andinhibiting the formation of an inversion layer or channel in thisvoltage range.

The incorporation of a low resistivity layer at the silicon-silicondioxide interface will also improve the resolution of the diode-arraytarget. The resolution ofa normal target is limited by lateral diffusionof the minority carriers as they diffuse from the light incident surfacetowards the depletion regions of the diodes. The thicker the target thegreater the loss of resolution. If the depletion regions of the diodescould be pushed back to the light incident surface, the minoritycarriers created by the incident photons would be in a strong electricfield region and there would be no possibility of lateral diffusion. Ina typical diode-array target, the nominal resistivity of the substrateis =lQ-cm, and with this resistivity the use of a target voltage highenough to push the depletion regions to the light incident surface isnot practical. A much higher substrate resistivity cannot be usedbecause then the target capacitance would be too small to provide themagnitude of the video signal usually required. With the low resistivityregion, a much higher substrate resistivity can be used since most ofthe target capacitance will consist of that provided by the lowresistivity region surrounding the p-regions of the diodes. With thisstructure, for a given target voltage, the depletion regions of thediodes will extend further back towards the light incident surface thanin a conventional target with a homogeneous substrate resistivity.

For example, if the depth of the low resistivity region is 2;; and thediode diameter is 8 then to obtain the same target capacitance as thatprovided by a homogeneous lOfl-cm substrate, assuming the majorcontribution to the target capacitance is the diode capacitance, alfl-cm surface region is possible with a substrate resistivity of=l00fl-cm. Then for a given target voltage, the depletion regions in thenew structure will extend back -33 times as far as in the conventionaltarget with a unifonn lOQ-cm substrate.

This improved resolution performance could be very important for targetsdesigned to operate in the wavelength range of 0.95 to 1.10 In thisrange, the absorption coefficient of Si decreases rapidly withincreasing wavelength, and to achieve a useable sensitivity, the targetmust be made relatively thick. As a result, the resolution with aconventional target structure would be very poor.

One limit to the improvement in resolution that can be obtained with athick target and a low resistivity surface layer is the requirement thatthe capacitance between diodes be small compared to the capacitancebetween the diodes and the undepleted substrate. If this is not thecase, the ability to produce a potential profile on the diode side ofthe array will be lost. This becomes a problem with thick targetsbecause as the depletion regions of the diodes are pushed back to thelight incident surface, the depletion regions of adjacent diodes maymerge underneath the low resistivity region causing the capacitancebetween the diodes and the undepleted substrate to become small. Toprevent this from occurring, the low resistivity region can be made toextend back to the light incident surface at isolated regions betweenthe diodes, thus preventing the depletion regions from adjacent diodesfrom merging.

These and other aspects of the invention will be explained more fully inthe following detailed description. In the drawmg:

FIG. 1 is a schematic view of a camera tube incorporating the improvedtarget;

FIG. 2 is a front sectional view showing, the target of FIG. 1;

FIGS. 3A and 3B are schematic representations illustrating theseparation between contiguous depletion regions in the prior artstructure (FIG. 3A) and the structure of the invention (FIGS. 38 and3C).

An exemplary electron beam device employing the improved target is shownin FIG. 1. The standard tube envelope 10 contains a cathode 11 andcathode heater 12. The control grid is shown at 13, accelerating grid14, wall accelerating grid 15, field mesh 16, and decelerating grid 17.All are biased at appropriate potentials known in the art. Alignmentcoil 18, deflecting coil 19 and focusing coil 20 are standard. Theimproved target 21 is shown in detail in FIG. 2. The semiconductorsubstrate 30 includes an array of diflused regions 31 forming p njunctions with the substrate. In the usual mode the substrate is n-typewith p-type diffused regions. The reverse configuration is useful whenoperating in the mesh stabilized mode. The surface of the semiconductoris covered with a dielectric layer 32 except for the windows used toform the diffused regions. The surface portion of the substrate 30between the diffused regions is provided with a low resistivity layer33. This layer is provided according to the invention to isolate eachdiode from others in the array and to improve the target performance asdescribed above.

in greater detail,

An important aspect of the invention is illustrated schematically inFIGS. 3A, 3B and 3C. FIG. 3A shows the conventional target structurewithout the low resistivity layer. The depletion layer 34 surroundingeach diffused region 31 extends into the corresponding region of theadjacent diode. Under adverse conditions, such as a defect causing highjunction leakage, inversion of the semiconductor surface will occur,adjacent pregions will be electrically connected and target resolutionwill be impaired.

In FIG. 3B the surface region of substrate 30 between diodes is providedwith a low resistivity layer 33. In this configuration this layer is N'.The depletion region 34 is now confined more closely to the physical p-njunction at and near the surface of the substrate 30. Surface generationis thereby reduced and inversion of this region becomes less likely.

FIG. 3C illustrates an embodiment similar to that of FIG. 38 withreference numerals denoting identical elements except that the N layerin this case extends to the image side of the target. As indicated abovethis permits the use of higher target voltages without merging under theN layer of the depletion regions of adjacent diodes.

, In a preferred embodiment of the invention the substrate 30 is n-typ'esilicon having a resistivity in the range of l to 100cm. The dielectriclayer 32 is SiO The p-diffused region and the N layer have impurityconcentrations, obtained by wellknown techniques, in the range of 1.10"to 5.10 atoms/cc. and preferably between and 10" atoms/cc. With higherimpurity concentration, breakdown between diodes is apt to occur. Alsothe diode capacity will be too great and excessive capacitive lag willresult. The lower limit is established to give the results illustratedby FIG. 3B.

Although this impurity concentration is obtainable with conventionaldiffusion techniques greater control and reliability are obtained byimplanting the impurities with an ion beam.

For example, approximately l0 /cm of P ions at 300 keV implanted intothe silicon substrate will produce a doped region with a projected rangeof ==4,000 A. and a straggling of =l,000 A. The target can then beprocessed in the normal manner with an 8,000 A. oxide grown, e.g., indry oxygen at 1 ,100 C for 40 minutes and annealed in nitrogen for onehour at 400 C.

Alternatively the N layer can be implanted after the growth of the oxideand the formation of the diodes. With an oxide 8,000 A. thick, l0""/cmof P at 600 keV produces the desired N region with the peak impurityconcentration at approximately the Si-SiO interface.

The target performance can be further improved by the addition of asemiresistive sea covering the side of the target exposed to theelectron beam. The addition of this layer eliminates localized chargeaccumulation that would otherwise interfere with proper beam landing.Useful materials for this layer are 500 to 10,000 A. of Sb S or 200 to1,500 A. of gallium arsenide.

Further improvements in target performance can be obtained by depositingconducting islands over the diode regions. For example gold islands ofthe order of 0.1 to lg. in thickness have been found to increase thediode capacitance thereby increasing the time constant and dynamic rangeof the target. If the islands are physically larger than the diode areas(e.g., 3,1. separation as compared with normal diode separation of 10 to1211,) then the beam landing efficiency in terms of the utilization ofelectron beam current is improved by the ratio of the beam landing areas(one-eighth to more than onehalf. If the islands are square the ratiobecomes nearly threefourths.)

Various additional modifications and extensions of this invention willbecome apparent to those skilled in the art. All such variations anddeviations which basically rely on the teachings through which thisinvention has advanced the art are properly considered Within the spiritand scope of this invention.

What is claimed is:

1. An electron beam storage device comprising in combination: a targetstructure comprising an n-type silicon wafer having a resistivity in therange of l ohm cm to ohm cm; an array of p-type impurity regions formedinto a surface of the wafer, each of said regions forming with the majorportion of the wafer a pn junction, an SiO dielectric layer covering then-type portion of the surface around the p-type regions, means forscanning the array of p-n junctions with the electron beam, and ann-type impurity region formed into the surface of the wafer between thearray of p-type impurity regions so as to surround each of the p-njunctions annularly, said region having a resistivity significantly lessthan the resistivity of the remaining n-type portion of the wafer and animpurity concentration of at least 10 atoms/cc. and extending throughthe thickness of the wafer.

2. The storage device of claim 1 in which the impurity regions and thedielectric layer are covered with 500 to 10,000 A. of Sb s 3. Thestorage device of claim 1 in which the impurity regions are covered with200 to 1,500 A. of gallium arsenide.

4. The storage device of claim 1 further including metal conductingislands covering each impurity region.

5. The storage device of claim 4 in which the metal conductive islandscomprise 0.1 to 1.0a of gold.

1. An electron beam storage device comprising in combination: a targetstructure comprising an n-type silicon wafer having a resistivity in therange of 1 ohm cm to 100 ohm cm; an array of p-type impurity regionsformed into a surface of the wafer, each of said regions forming withthe major portion of the wafer a p-n junction, an SiO2 dielectric layercovering the n-type portion of the surface around the p-type regions,means for scanning the array of p-n junctions with the electron beam,and an n-type impurity region formed into the surface of the waferbetween the array of p-type impurity regions so as to surround each ofthe pn junctions annularly, said region having a resistivitysignificantly less than the resistivity of the remaining n-type portionof the wafer and an impurity concentration of at least 1016 atoms/cc.and extending through the thickness of the wafer.
 2. The storage deviceof claim 1 in which the impurity regions and the dielectric layer arecovered with 500 to 10,000 A. of Sb2S3.
 3. The storage device of claim 1in which the impurity regions are covered with 200 to 1,500 A. ofgallium arsenide.
 4. The storage device of claim 1 further includingmetal conducting islands covering each impurity region.
 5. The storagedevice of claim 4 in which the metal conductive islands comprise 0.1 to1.0 Mu of gold.